Control of topography and morphology for channel SiGe by in-situ HCl etching for future CMOS technologies with high-K metal gate

In high-K metal gate-first integration for future CMOS technologies an epitaxial SiGe layer in the P-channel is applied to modulate VT. This results in an unwanted elevation of the P-channel challenging particularly gate patterning. In this work, an in-situ HCl etching process prior to deposition of the channel SiGe for gate-first integration of HKMG has been studied. By in-situ HCl etching prior to epitaxial deposition (recessed cSiGe) the topography is clearly reduced with excellent epitaxial quality. The morphology of channel SiGe particularly for very small feature sizes is significantly improved by recessing the P-channel prior to epitaxial deposition. The flat topography shows a clear benefit for the gate-first integration. The topography driven P-channel leakage was reduced by one order of magnitude for recessed channel SiGe.

Research highlights
► A SiGe epi layer in the P-channel is applied to modulate VT.
► This results in an unwanted elevation of P-channel.
► In-situ HCl etching prior to epi deposition reduces topography.
► Topography driven leakage current has been reduced by one order of magnitude.