Behavior of triple-gate Bulk FinFETs with and without DTMOS operation

In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristics and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications.

► Dynamic Threshold (DT) voltage technique in triple-gate FinFETs.
► Standard Bulk FinFETs and Bulk FinFETs under DTMOS operation.
► DTMOS technique is a good alternative to standard low-power low-voltage devices.
► DTMOS technique advantage is due to its ability to adjust the threshold voltage.
► In DTMOS operation, the back gate plays the role of an additional gate.