Drain bias dependent bias temperature stress instability in a-Si:H TFT

The threshold voltage (Vt) instability of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) is investigated under drain bias dependent bias temperature stress (VD-BTS). The drain bias reduces the overall gate overdrive stress and leads to a position-dependent Vt-shift (ΔVt) with maximum ΔVt at the source-end and minimum ΔVt at the drain-side of channel. Measured ΔVt was compared with the calculated ΔVt using a weighted average of local Vt-shift. The calculated ΔVt based on weighted average agreed better with the measured data in U-type samples, but a simple linear average over the channel agreed better with the measured data in an I-type sample. This is explained in terms of the fact that the source-side channel width is larger than the drain-side width in a U-type sample which results in more contribution from the source-side to the normalized ΔVt. A non-uniform Vt profile due to VD-BTS resulted in a higher drain current in the forward measurement (source/drain are the same as in stress) than in reverse measurement (source/drain are interchanged from stress). This also leads to a different extracted Vt in forward and reverse configurations due to the non-uniform Vt profile along the channel. Vt extracted from the saturation transfer curve varies significantly in different current ranges due to the gate bias dependence of field-effect mobility caused by a large variation of the overdrive voltage along the channel.