Compact modeling of CMOS transistors under variable uniaxial stress

This paper presents a novel implementation of variable uniaxial mechanical stress model to be used with DC circuit simulation, e.g. using BSIM3v3 transistor model. Based on transistor measurements under various uniaxial stress conditions two stress-dependent parameters are identified, namely the carriers mobility and to a lesser extend the carrier saturation velocity. The effect of the parasitic source/drain resistance on the piezoresistive coefficient determination is addressed in detail. Using the fundamental piezoresistive coefficients, the model has implemented a general relation to calculate the coefficients for arbitrary directions of current and stress in the (0 0 1) silicon (Si) plane. The extended transistor model allows for simulating the effect of uniaxial stress on any MOSFET geometry, under different operation conditions and for any combination of the drain current and stress orientations in the (0 0 1) silicon (Si) plane. The method proposed in this paper is validated by static and dynamic stress-dependent simulations and comparison with experimental data. The method is simulator-independent and can be adapted to other bulk CMOS technologies including SOI processes.

Research highlights
► We propose a method to simulate the effect of uniaxial stress on MOSFETs.
► The method is valid for any drain current and stress directions in (001) Si plane.
► It can perform static and dynamic simulations, in linear and saturation regions.
► It is simulator-independent and does not depend on the source of uniaxial stress.
► It is adaptable to other bulk CMOS nodes and to other technologies such as SOI.