Repeating of positive and negative high electric field stress and corresponding thermal post-stress annealing of the n-channel power VDMOSFETs

We have subjected n-channel power VDMOSFETs to a positive and negative high electric field stress (HEFS) followed by biased annealing at 150 °C. Stress-induced defects have been monitored using midgap-subthreshold and charge-pumping techniques, the use of which in tandem has enabled an insight into behaviours of fixed and switching traps in the gate oxide and oxide/silicon interface. The repetition of the stress/annealing sequence has resulted in some quantitative but no qualitative differences in response compared to the original sequence. We have observed complex kinetics of different types the stress-induced defects during post-HEFS annealing, including an intriguing latent buildup of “true” interface traps. Comparison of post-HEFS and post-irradiation annealing data has indicated differences of the nature of defects induced by Fowler-Nordheim injection and irradiation in our samples.