Physical insights on nanoscale multi-gate CMOS design

Several studies of multi-gate silicon MOSFETs are overviewed to convey physical insights on the (front-end) design of nonclassical nanoscale CMOS. The studies imply that double-gate (DG) FinFETs have mainstream potential, and the suggested device designs are pragmatic and doable. Numerical device simulations and UFDG/Spice3 device/circuit simulations suggest that pragmatic DG-FinFET CMOS can be optimally designed to yield outstanding performances in all applications, with good tradeoffs between speed and power consumption as the gate length is scaled to less than 10 nm.