کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
7939197 | 1513188 | 2018 | 23 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی مواد
مواد الکترونیکی، نوری و مغناطیسی
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior](/preview/png/7939197.png)
چکیده انگلیسی
The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Superlattices and Microstructures - Volume 113, January 2018, Pages 57-70
Journal: Superlattices and Microstructures - Volume 113, January 2018, Pages 57-70
نویسندگان
Vandana Kumari, Ayush Kumar, Manoj Saxena, Mridula Gupta,