Effect of trench depth and gate length shrinking assessment on the analog and linearity performance of TGRC-MOSFET

This paper discusses the impact of trench depth (Negative Junction Depth (NJD)) and gate length (LG) shrinking on analog and linearity performance of Transparent Gate Recessed Channel (TGRC) MOSFET with an aim to achieve a reliable and high performance transistor. It is found that device enhances the ION by 38% and thereby improves the analog performance in terms of transconductance, device efficiency, output resistance, and gain. Moreover, linearity figure of merits are also enhanced at lower gate bias in TGRC MOSFET in comparison to conventional and Conventional Recessed Channel (CRC) MOSFET due to reduced harmonic distortions (gm3). Thus, the improved analog and linearity performance at 5 nm NJD and 20 nm LG of TGRC-MOSFET makes it suitable for low power linear RF amplifiers as a nano-scaled device. Thus, these results would serve as a worthy design tool for low power and high performance CMOS circuits.