Ni fully silicided gates for 45Â nm CMOS applications

The Ni silicide phases and morphology in Ni fully silicided gates was investigated for varying deposited Ni to Si thickness ratios and rapid thermal processing conditions. The presence of NiSi2, NiSi, Ni3Si2, Ni2Si, Ni31Si12 and Ni3Si as predominant phases was observed for increasing Ni to Si thickness ratios. In most samples, typically two of these phases were detected by X-ray diffraction. No secondary phases were detected on Ni3Si samples (Ni to Si thickness ratio ∼1.7). For samples targeting NiSi as gate electrode, RBS and TEM analysis confirmed a layered structure with NiSi at the interface and a Ni-rich silicide layer (Ni2Si, Ni3Si2) on top. Process conditions were determined for the formation of gate electrodes for NiSi, Ni2Si and Ni3Si. Only small changes in flat-band voltage or work function were found between these phases on SiO2 or SiON for undoped samples. While significant changes in work function with dopants were observed for NiSi on SiO2, little or no effects were found for NiSi on HfSiON (suggesting Fermi-level pinning) and for Ni2Si on SiO2. An increase of >300 mV was found from NiSi to Ni3Si on HfSiON, suggesting unpinning of the Fermi level with the Ni-rich silicide.