کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
9670355 | 1450401 | 2005 | 7 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Optimization of shear test for flip chip solder bump using 3-dimensional computer simulation
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله

چکیده انگلیسی
The shear test for flip chip solder bump was investigated in terms of effects of test parameters, i.e., shear height and shear speed, with an experimental and non-linear 3-dimensional finite element analysis for evaluating the solder joint integrity of area array packages. A representative Pb-free, Sn-3.0Ag-0.5Cu, was examined in this study. It could be observed that increasing shear height, at fixed shear speed, has the effect of decreasing shear force, while the shear force increased with increasing shear speed at fixed shear height. Relatively high shear height exceeding about 20% of the solder bump height could cause some unfavorable effects on the test results such as unexpected high standard deviation values or shear tip sliding from the solder bump surface. The low shear height conditions were favorable for screening the type of premature brittle interfacial fractures or the degraded layers in the interfaces. The increase in shear force with the shear speed is highly related with the stress values of the von Mises stress contours within the solder bump.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronic Engineering - Volume 82, Issues 3â4, December 2005, Pages 554-560
Journal: Microelectronic Engineering - Volume 82, Issues 3â4, December 2005, Pages 554-560
نویسندگان
Jong-Woong Kim, Seung-Boo Jung,