Electron beam lithography for nanometer-scale planar double-gate transistors

Double-gate transistors are promising successors to conventional bulk MOSFETs, since their gate arrangement limits short channel effects yielding better device performance, even at nanometer size gate lengths. An electron beam lithography process for patterning and aligning the nanometer-size gates of a planar double-gate transistor has been constructed. The gates are structured non self-aligned on both sides of a thin c-Si layer, whereby the first structured gate layer together with the c-Si layer is transferred to a handling wafer using wafer bonding and wafer back-side etching, enabling access to the backside of the c-Si layer. Top and bottom gates have been aligned with 25 nm accuracy using topographic marks that are detectable in both exposure steps. Gate lengths of less than 20 nm were structured using the hydrogen-silesquioxane (HSQ) resist. With the help of Monte Carlo simulations the optimal electron acceleration voltage was determined to obtain the best resolution possible when patterning top and bottom gates. An intra-proximity correction was introduced for the acceleration voltage used by varying the dose factor of every pattern to be written.