Lateral scaling challenges for SiGe NPN BiCMOS process integration

Lateral scaling was employed to achieve high-speed NPN bipolar performance, and specifically the role of active scaling was investigated. As function of active design rule over-plot emitter window, two collector implant designs are compared in a self-aligned emitter integration scheme. Decreasing design rule significantly decreases collector-base capacitance as a result of greater isolation from the extrinsic base. Non-selective SiGe epi process integration is susceptible to deleterious facet growth at the active edge, which can compromise the base resistance and negate any overall Fmax gain. An optimization of design rule and fabrication are presented for nominal 200 GHz Ft devices; the Fmax gain was improved from 165 to 215 GHz. Normal DC output characteristics and a BVceo of 2.4 V facilitate modular integration within 1.2 or 1.8 V core BiCMOS technology nodes.