Effect of deep cryogenic temperature on silicon-on-insulator CMOS mismatch: A circuit designer’s perspective

• CMOS mismatch at very low temperature compared to room temperature is quantified.
• 4 K matching is largely uncorrelated to that at 300 K, further investigation required.
• Threshold voltage variation at 4 K is approximately twice as much of that at 300 K.
• Current factor mismatch at 4 K has strong dependency on drain–source and gate voltage.
• Common layout techniques may not provide matching benefits at 4 K operation.

The effect of ultra low operating temperature on mismatch among identically designed Silicon-on-Sapphire CMOS devices is investigated in detail from a circuit design view point. The evolution of transistor matching properties for different operating conditions at both room and 4.2 K temperature are presented. The statistical analysis reveals that mismatch at low temperature is effectively unrelated to that at room temperature, which disagrees with previously published literature. The measurement data was used to extract key transistor parameters and the consequence of temperature lowering on their respective variance is estimated. We find that standard deviation of the threshold-voltage mismatch deteriorates by a factor ∼∼2 at 4.2 K temperature. Similar to room temperature operation, mismatch at 4.2 K is bias point dependent and the degradation of matching at very low temperature depends to some extent on how the bias point shifts upon cooling.