کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
1552496 1513204 2016 15 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Performance optimization of nanoscale junctionless transistors through varying device design parameters for ultra-low power logic applications
ترجمه فارسی عنوان
بهینه سازی عملکرد ترانزیستورهای نانومقیاس بدون اتصال از طریق پارامترهای مختلف طراحی دستگاه برای برنامه های کاربردی منطق بسیار کم قدرت
موضوعات مرتبط
مهندسی و علوم پایه مهندسی مواد مواد الکترونیکی، نوری و مغناطیسی
چکیده انگلیسی


• Low power performance of nanoscale junctionless (JL) MOSFETs is optimized.
• Impact of channel doping, underlap spacer, etc. on performance metrics is studied.
• ON-current for a fixed OFF-current, subthreshold swing & delay are optimized.
• Our proposed JL MOSFETs outperform Si FinFETs at channel length of 34 nm.

Ultra-low power logic applications at advanced CMOS technology nodes have been extensively investigated nowadays to increase packing density in Integrated Circuits at a lower cost. Junctionless (JL) transistors have emerged as promising alternatives to conventional MOSFETs because of their relatively easy fabrication steps and extreme scalability. We perform a detailed numerical study to evaluate the effects of channel doping concentration, dielectric constant of underlap spacers, source/drain resistance on logic performance of 20 nm gate length JL MOSFETs in terms of ON-current at a given OFF-current, subthreshold swing, gate capacitance and intrinsic delay for supply voltages ranging 0.4–0.75 V. In comparison with the reported experimental data for inversion-mode device, our optimized JL device exhibits enhancement of ION by 15.6%, reduction of drain-induced barrier lowering (DIBL) by 22.5% while preserving equally low SS of 61.5 mV/decade at channel length of 34 nm and supply voltage of 0.75 V.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Superlattices and Microstructures - Volume 97, September 2016, Pages 140–154
نویسندگان
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