A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping

• A new δ-doped cylindrical gate silicon tunnel FET (DCG-TFET) analytical model is proposed.
• The effect of distance from tunneling junction on drain current, SS and Vth has been examined.
• The distance is optimized based on the trade-off between current switching ratio and SS.
• The present model exhibit high switching current ratio for an optimum distance of 2 nm.

A new δ-doped cylindrical gate silicon tunnel FET (DCG-TFET) analytical model is developed and investigated extensively, with the aim of addressing the challenges of the conventional CG-TFET. The improvement in tunneling probability of charge carriers has been achieved by inserting a δ-doping sheet in the source region which leads to high drain current as compared to CG-TFET. The effect of distance between the δ-doping sheet and source/channel interface on the current performance, sub-threshold swing (SS) and threshold voltage (Vth)(Vth) has been examined. The instantaneous position of δ-doping region from the tunneling junction is optimized based on the trade-off between current ratio and SS. The present model exhibit maximum switching current ratio (IONIOFF≅1012) for an optimum distance of 2 nm without degrading SS (SS∼55 mV/decade) and Vth performance. The electrostatic behavior of the present model is obtained using the solution of Poisson’s equation in the cylindrical coordinate system. However the impact of scaling of the gate oxide thickness and cylindrical pillar diameter on drain current performance has been discussed. In future, DCG-TFET can be one of the potential successors for ultra-low-power applications because of its improved drain current and switching ratio.