Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate

In this work, we have developed a two-dimensional (2-D) analytical drain current model for cylindrical-gate tunnel FET structure with linearly graded binary metal alloy gate. The surface potential of the proposed model is determined using the solution of 2-D Poisson's equation with suitable boundary conditions. Further it paves way for the calculation of other analog parameters such as shortest tunneling distance, drain current, threshold voltage and subthreshold swing (SS). The introduction of linearly modulated work-function of binary alloy optimizes the subthreshold swing by ∼10 mV/decade as compared to conventional cylindrical-gate tunnel FET devices without degrading the drain current and threshold voltage performance. Also the present model shows the reduction in SS with down-scaling of gate oxide thickness and silicon pillar diameter. The analytical results are found to be synonymous with the results of Synopsys TCAD device simulator.