Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation

In this work, the performance comparison of two heterojunction PIN TFETs having Si channel and Si0.5Ge0.5 source with high-k (SiGe DGTFET HK) and hetero-gate dielectric (SiGe DGTFET HG) respectively with those of two homojunction Si based PIN (DGTFET HK and DGTFET HG) TFETs is performed. Similarly, by employing the technique of pocketing at source junction in above four PIN TFETs, the performances of resultant four PNPN TFETs (SiGe PNPN DGTFET HK, SiGe PNPN DGTFET HG, PNPN DGTFET HK and PNPN DGTFET HG) are also compared with each other. Due to lower tunnel resistance of SiGe based heterojunction PIN and PNPN TFETs, the DC parameters such as ON current, ON-OFF current ratio, average subthreshold slope are improved significantly as compared to Si based PIN and PNPN TFETs respectively. The output characteristics of HG architectures in Si based homojunction PIN and PNPN TFETs is observed to be identical to with respective Si based HK PIN and PNPN TFET architectures. However, the output characteristics of HG architectures in SiGe based heterojunction PIN and PNPN TFETs degrade as compared to their respective SiGe based HK PIN and PNPN TFET architectures. In ON state, SiGe based HK and HG PIN and PNPN TFETs have lower gate capacitance (Cgg) as compared to their respective Si based HK and HG PIN and PNPN TFETs. Moreover, HG architecture suppresses gate to drain capacitance (Cgd) and ambipolar conduction. Transconductance (gm) and cut off frequency (fT) is also observed to be higher for SiGe based PIN and PNPN TFETs.