Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics

• An attempt to characterization of TCP/ZTC point of UT-SDOI SG, DG and GS-DG, n-MOSFET.
• The interface trapped charges during the pre and post fabrications process are considered in the simulation.
• Characterization of various performance metrics over wide range of temperatures (100–400 K).
• DC, Analog and RF (both static and dynamic) figures of merit (FOMs) are analyzed.
• A promising solution to minimize the temperature degradation of RF circuits.

An inflection point on the behaviour of MOSFET over wide range of temperatures (T) influences performance of both analog and digital circuits. This work is an investigation to find the point of inflection at which the temperature coefficient is zero of Ultra-Thin Si directly on Insulator (UT-SDOI) single gate (SG), double gate (DG), and gate stack double gate (GS-DG), n-MOSFET over wide range of temperatures (100–400 K) through 2-D device simulation. The interface trapped charges which are common during the pre and post fabrication process are also considered in the simulation. The impact of T on various performance metrics like on current (Ion), off current (Ioff), on–off current ratio (Ion/Ioff), subthreshold slope (SS), Q-factor, intrinsic gate delay (τ), energy delay product (E⋅τ), transconductance (gm), output conductance (gd), intrinsic gain (AV), cut off frequency (fT) and sweet spot have been analyzed extensively to benchmark the device behaviour. The impact of temperature compensation point (TCP) over various performances for three typical devices is compared. This validates an opportunity for nanoscale MOSFETs in designing the circuits used for various applications.