The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors

At nanometer regime, fabricating the structures with non-overlapped channel and abrupt doping profile is very complicated and sometimes impossible. So, the resultant device experiences some non-ideal effects which have to be predicted and well addressed by simulation before fabrication. In this paper the effects of overlap between gate and source/drain regions on the performance of carbon nanotube field effect transistors have been investigated. The overlapped structure has been simulated with various doping profiles at drain/source and gate region junction tip. The device performance has been investigated in terms of ON current, Off current, ON/Off current ratio, subthreshold swing, delay, and power delay product (PDP). Simulations show that depending on the variations in the effective channel length, the overlap deteriorates some device characteristics and enhances the others. Where the effective channel length decreases (increases), the overlap deteriorates (enhances) the current ratio and subthreshold swing but enhances (deteriorates) the delay and PDP compared to non-overlapped structure. Furthermore, the overlapped structure with graded profile results in lower current ratio and higher subthreshold swing compared to overlapped structure with abrupt profile. At a fixed current ratio, the delay and PDP of overlapped structure with graded profile are more than overlapped structure with abrupt profile but at a fixed channel length, both profiles have approximately equal delay and PDP.

Simulations show that depending on the variations in the effective channel length, the overlap deteriorates some CNTFET characteristics and enhances the others.Figure optionsDownload as PowerPoint slideHighlights
► Effects of gate and source/drain regions overlap on CNTFETs have been investigated.
► Overlapped structure simulated with abrupt/graded doping profiles.
► The overlap changes effective channel length.
► Device characteristics variations depend on variations in effective channel length.
► The overlap impresses device speed and PDP by variation in junction capacitances.