The illustrated brief application of defect distribution model for heterojunction device by admittance spectroscopy

The dielectric properties of the devices can be studied by using admittance spectroscopy (AS). Majority carrier traps are experimentally analyzed without sophisticated mathematical manipulation. Experimental evidence obtained from AS of the devices may display several features that cannot be explained by the usual single RC circuits representing a depleted junction region and undepleted bulk elements. In this study, ac behavior of typical pn junction diode is simulated using temperature depended AS in a broad frequency range (5 Hz to 13 MHz). The frequency-dependent admittance data of typical pn junction has been discussed based on a discrete deep or shallow trap model. The analytically obtained frequency depended −dC/dω and tan δ (loss tangent) curves are peaks function. The position of the peak depends on the temperature and dc-bias. This peak position gives us information about deep or shallow trap states. The trapping time and trap energy levels can be deduced from −dC/dω versus ω or tan δ versus ω curves. This investigation shows that suitable complex admittance measurement data obtained during the capacitance–voltage measurement process are used to calculate the trapping time and energetic position of the traps. A theoretical analysis and computer simulation are presented in order to illustrate the nature of the trap and the technique by which accurate trapping time and energy position of the trap state can be obtained.

► Admittance data are used to determine shallow or deep energy levels in heterojunction device.
► We have suggested new equivalent circuit for heterojunction device to mimic the traps.
► The used analytical model is good formulation for display exact energetic location of traps.