Optimization of through silicon via for three-dimensional integration

• The vias fabrication and copper vias filling in TSV process are optimized.
• The etch/passivation recipe is modified to eliminate the micrograss successfully.
• Vacuuming is efficient to improve the wettability of TSV with copper electrolyte.
• An improved two-step electroplating process is proposed during electroplating.

Three-dimensional integration has drawn more and more attention in electronics industry due to its potential of reducing the interconnect delay, improving the device performance and realizing heterogeneous integration, where through silicon via has become the mainstream. In this paper, the key technologies including via fabrication and copper via filling in the through silicon via process were investigated and optimized. We analyzed the micrograss on the via sidewall that would create sidewall profile issues, and modified the etch/passivation recipe to eliminate the micrograss. Vacuuming before electroplating to enhance the wettability of the through silicon via with copper electrolyte was introduced. Magnetic stirring was performed and an improved two-step electroplating process was applied during electroplating. With these optimized processes, we demonstrated defect-free copper filled through silicon vias with shorter plating time and thinner copper overburden on the wafer surface, which is beneficial to the realization of three-dimensional integration.

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