Gate-induced drain leakage in FD-SOI devices: What the TFET teaches us about the MOSFET

This paper compares the gate-induced drain leakage (GIDL) in fully-depleted (FD) silicon-on-insulator (SOI) tunneling field effect transistor (TFET) and in standard metal-oxide-semiconductor FET (MOSFET) fabricated in the same process. The measurements show that the MOSFET GIDL current is lower than the GIDL in a TFET with the same junction doping, especially for devices with thick gate oxide and under low drain bias. A model describing lateral band-to-band tunneling (BTBT) is developed for GIDL in the FD-SOI TFET. By combining the model of gate-controllable tunneling diode in series with a field effect diode, we achieve an accurate picture of GIDL in FD-SOI MOSFETs.

The GIDL in TFETs can be modeled by considering only the drain-channel tunneling diode. In FD MOSFETs, the source-channel field effect diode should also be included leading to lower GIDL current than in TFETs.Figure optionsDownload as PowerPoint slideHighlights
► Gate-induced drain leakage (GIDL) current in TFETs is higher than that in FD MOSFETs, especially under low drain bias.
► GIDL in TFETs can be accurately modeled by considering the gated tunneling junction only, whereas GIDL in MOSFETs requires the addition of a field effect diode (FED) component.
► Stronger GIDL temperature dependence in FD MOSFETs compared to TFETs, confirms the importance of the FED component.