Electrical properties of self-aligned gate-all-around polycrystalline silicon nanowires field-effect transistors

Low temperature (≤ 600 °C) polycrystalline silicon nanowires field-effect transistors have been developed following a top-down approach and classical photolithography techniques. N channel transistors have been tested with a single top-gate, bottom-gate and gate-all-around architecture in order to compare their electrical performances in relation to the interface state density. Analysis shows that surrounding gate enables control of parameters such as on-current, subthreshold slope and threshold voltage and offer potential further applications.

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