Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration

In this paper we will highlight key integration issues that were encountered during the development of the 3D-stacked IC Through Silicon Via (TSV) module and present solutions to achieve a robust copper TSV. Electrical performance of the obtained TSV module is discussed based on a lumped RC model for 3D ring oscillators containing TSVs between bottom and top tiers.