A novel hierarchical architecture for Wireless Network-on-Chip

In the architecture of Networks-on-Chip (NoCs), wired structure and multi-hop communications can lead to high power consumption and latency. Wireless NoC (WiNoC) architecture is a new alternative to solve these challenges. In this architecture, long-range wireless links are used instead of multi-hop wired paths. In this paper, a combination of several topologies are investigated to develop an efficient hierarchical structure for the architecture of WiNoC. The performances of considered hierarchical structures are compared under different traffic patterns. Finally, by using the Analytic Hierarchy Process (AHP) technique, a new hierarchical wireless NoC is proposed. In the proposed architecture, hierarchical structure and wireless links with high bandwidth are regarded as two significant factors for reducing the number of hops between distant nodes. Based on the results of simulations, the proposed hierarchical structure has better efficiency than other WiNoC architectures.