Fabrication of through-silicon vias by supercritical CO2 emulsion-enabled nickel electroplating

Compared to the 2D plane, 3D integrated circuit (IC) structure could provide larger patterning areas by stacking the multi-planar chips, in which the electrical signals can be vertically conducted via through-silicon vias (TSVs). Thus, its advantages are lowered costs and reduced packaging space, size and weight. In this study, the TSVs used for 3D integration are fabricated and characterized. Four through holes with a diameter of 70 μm on a silicon wafer are first etched by inductively coupled plasma reactive ion etch (ICP) and filled by nickel electroplating in supercritical CO2 emulsion. The chip is cut for observation and examination of the cross-sectional view of the TSVs. For hermeticity testing, a helium leaking detector was performed on all TSVs before and after the heat treatment process (heating up to 350 °C). The average electrical resistance across the TSVs was measured to be 0.01 Ω. Then the fabricated TSVs can be applied a maximum current of 10 A continuously without burnout.