The origin of forward bias capacitance peak and voltage dependent behaviour of gold/p-type indium phosphide Schottky barrier diode fabricated by photolithography

The admittance measurements which include the capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of gold/p-type indium phosphide (Au/p-InP) Schottky barrier diodes (SBDs) were conducted by taking into account the interface states (Nss) and series resistance (Rs) effects in the temperature range of 80–320 K with a steps of 20 K. Experimental results confirm that the Nss and Rs are important parameters which strongly influence the main electrical parameters of SBD. The C–V plots for each temperature exhibit the increasing behaviour in depletion region and then give an anomalous peak such that peak position shifts toward positive bias region with increasing temperature due to the re-structuring and re-ordering of surface charge under the temperature effect and the existence of a series resistance (Rs). In addition, C takes negative values in the inversion region at edge, which is known as negative capacitance (NC) behaviour. The effect of Rs on the C–V plot is found considerably high at low temperatures in the accumulation region. Therefore, both the measured capacitance (Cm) and conductance (Gm/ω) were corrected to obtain the real diode capacitance (Cc) and conductance (Gc/ω). In addition, Rs and Nss values decrease with increasing temperature. Such behaviour of Rs and Nss can be attributed to the trap charges which have sufficient energy to escape from the traps located at gold/p-type indium phosphide (Au/p-InP) interface.