کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
7939626 | 1513189 | 2017 | 22 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی مواد
مواد الکترونیکی، نوری و مغناطیسی
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
A novel ultra-low specific on-resistance (Ron,sp) trench lateral double-diffused MOSFET with P/N pillars and dual trench gates (P/N DTG-T LDMOS) based on silicon-on-insulator technology is proposed in this paper. The new structure features dual trench gates and heavily doping P/N pillars. The P/N pillars are inserted into the drift region under the P-well. The P-pillar causes an assistant depletion effect on the drift region. The N-pillar can not only improve the breakdown voltage (BV) by modulating the electric field but also significantly reduce the Ron,sp by increasing the doping concentration of the drift region. Furthermore, the dual trench gates form dual conduction channels and the heavily doping N-pillar provides a lower resistance region for the carriers, which can both reduce the Ron,sp. Consequently, compared with the conventional trench LDMOS, a lower Ron,sp of 0.58 mΩ cm2 and a higher the figure of merit (FOM, FOM=BV2/Ron,sp) of 62.9 MW/cm2 are obtained for the P/N DTG-T LDMOS, which are improved by 74.8% and 308.4% respectively. Meanwhile, the BVs of the both structures are maintained at a same level of 190 V.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Superlattices and Microstructures - Volume 112, December 2017, Pages 269-278
Journal: Superlattices and Microstructures - Volume 112, December 2017, Pages 269-278
نویسندگان
Dong Yang, Shengdong Hu, Jianmei Lei, Ye Huang, Qi Yuan, Yuyu Jiang, Jingwei Guo, Kun Cheng, Zhi Lin, Xichuan Zhou, Fang Tang,