کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
7940111 | 1398534 | 2017 | 31 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی مواد
مواد الکترونیکی، نوری و مغناطیسی
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers](/preview/png/7940111.png)
چکیده انگلیسی
Using extensive numerical analysis we investigate effects of asymmetric sidewall spacers on various device parameters of 20-nm double gate MOSFETs associated with analog/RF applications. Our studies show that the device with underlap drain-side spacer length LED of 10 nm and source-side spacer length LES of 5 nm shows improvement in terms of the peak value of transconductance efficiency, voltage gain Av, unity-gain cut-off frequency fT and maximum frequency of oscillations fMAX by 8.6%, 51.7%, 5% and 10.3%, respectively compared to the symmetric 5 nm underlap spacer device with HfO2 spacer of dielectric constant k = 22. Additionally, a higher spacer dielectric constant increases the peak Av while decreasing both peak fT and fMAX. The detailed physical insight is exploited to design a cascode amplifier which yields an ultra-wide gain bandwidth of 2.48 THz at LED = 10 nm with a SiO2 spacer.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Superlattices and Microstructures - Volume 110, October 2017, Pages 114-125
Journal: Superlattices and Microstructures - Volume 110, October 2017, Pages 114-125
نویسندگان
Debapriya Roy, Abhijit Biswas,