Drain Current Model for Double Gate (DG) p-n-i-n TFET: Accumulation to Inversion Region of Operation

In this paper, drain current model has been formulated for Double Gate (DG) p-n-i-n Tunnel FET (TFET) using Lambert-W function. The model includes the impact of mobile charges, gate dielectric thickness (tox) and channel thickness (tsi) on quasi fermi level, gate threshold voltage (VTG), onset voltage (VGonset) and Tunneling Barrier Width (TBW) over the entire operating range i.e. accumulation to inversion state. Important electrostatic and electrical parameters such as the effective potential (φeffective) at the center of the channel, 2-D channel potential, electric field, energy band profile and Tunneling Barrier Width (TBW) dependent drain current have been modeled. Moreover, gate and drain bias controllability in different operating regimes has also been investigated by varying oxide thickness (tox), channel thickness (tsi), intrinsic channel length (Lint) and at different temperatures. Important FOMs required for analog circuit performance such as transconductance (gm), drain conductance (gd), output resistance (Rout), early voltage (VEA) have also been evaluated and verified using ATLAS device simulation software.