Charge trapping in MOSFETs with HfSiON dielectrics during electrical stressing

Hafnium silicate had been suggested as a possible 'mid-k' alternative to SiON as a gate dielectric for the 45 nm technology node. This work focuses on the shift in threshold voltage, the degradation in transconductance, and the sub-threshold swing during oxide stress. Analysis of these parameters reveals much about the trap generation mechanisms in the layers, as well as differences from SiON. The effect of the aspect ratio dimensions on post-breakdown device functionality is also discussed.