کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
1544444 1512882 2015 9 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study
موضوعات مرتبط
مهندسی و علوم پایه مهندسی مواد مواد الکترونیکی، نوری و مغناطیسی
پیش نمایش صفحه اول مقاله
Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study
چکیده انگلیسی


• For the first time, channel-center based analytical model of gate-engineered junctionless surrounding gate (JLSRG) MOSFET.
• Comparative study between Triple-Material JLSRG and Dual-material JLSRG devices to suppress short-channel effects.
• Impact of gate-engineering on quantities like threshold voltage, surface potential, Electric Field, DIBL and subthershold swing.

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.

For the first time, channel-center based analytical model of gate-engineered junctionless surrounding gate (JLSRG) MOSFET to study the effect of gate-engineering on JLSRG devices.Figure optionsDownload as PowerPoint slide

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Physica E: Low-dimensional Systems and Nanostructures - Volume 67, March 2015, Pages 143–151
نویسندگان
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