Impact of gate length and barrier thickness on performance of InP/InGaAs based Double Gate Metal–Oxide-Semiconductor Heterostructure Field-Effect Transistor (DG MOS-HFET)

In this paper, we have analyzed the performance of InP/InGaAs heterostructure Double Gate MOSFET for variation of gate length (Lg) and barrier thickness (tb), using 2D sentaurus TCAD simulation. Drift-diffusion model was taken for simulating the proposed device. The gate length was varied from 12 nm to 30 nm and barrier thickness was changed from 1 nm to 3 nm. As gate length is reduced for scaling, higher drain current is achieved but at the expense of degraded DIBL and SS, furthermore, threshold voltage, Ion/Ioff, intrinsic delay and energy delay product are reduced. As barrier thickness is increased, there is an increase in DIBL, SS, intrinsic delay, energy delay product, while threshold voltage and Ion/Ioff decrease. Except SS and Ion/Ioff all other parameters are acceptable, a needful to improve the two parameters. However, the proposed device is ultimate to replace the MOSFETS for high speed application in the future.

► Impact of Lg and tb on SCE.
► Parameter analyzed DIBL, SS, Ion/Ioff, Vth, ID, EDP.
► 2D sentaurus TCAD simulation calibrated with experimental data.
► Decrease of Lg results in decrease in Vth, Ion/Ioff, delay, EDP.
► As tb is increased, increase in DIBL, SS, delay, EDP is observed.