Investigating the degradation behavior under hot carrier stress for InGaZnO TFTs with symmetric and asymmetric structures

This letter studies the hot-carrier effect in indium–gallium–zinc oxide (IGZO) thin film transistors with symmetric and asymmetric source/drain structures. The different degradation behaviors after hot-carrier stress in symmetric and asymmetric source/drain devices indicate that different mechanisms dominate the degradation. Since the C–V measurement is highly sensitive to trap states compared to the I–V characterization, C–V curves are utilized to analyze the hot-carrier stress-induced trap state generation. Furthermore, the asymmetric C–V measurements CGD (gate-to-drain capacitance) and CGS (gate-to-source capacitance) are used to analyze the trap state in channel location. The asymmetric source/drain structure under hot-carrier stress induces an asymmetric electrical field and causes different degradation behaviors. In this work, the on-current and subthreshold swing (S.S.) degrade under low electrical field, whereas an apparent Vt shift occurs under large electrical field. The different degradation behaviors indicate that trap states are generated under a low electrical field and the channel-hot-electron (CHE) effect occurs under a large electrical field.

► Asymmetric structure thin film transistors improve kick-back effect.
► Asymmetric structures under hot-carrier stress induce different degradation.
► Hot-carrier stress leads to capacitance–voltage curve distortion.
► Extra trap states are generated during hot-carrier stress.