Generation of uniaxial tensile strain of over 1% on a Ge substrate for short-channel strained Ge n-type Metal–Insulator–Semiconductor Field-Effect Transistors with SiGe stressors

Tensile strain of over 1% in Ge stripes sandwiched between a pair of SiGe source-drain stressors was demonstrated. The Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET)-like structures were fabricated on a (001)-Ge substrate having SiO2 dummy-gate stripes with widths down to 26 nm. Recess-regions adjacent to the dummy-gate stripes were formed by an anisotropic wet etching technique. A damage-free and well-controlled anisotropic wet etching process is developed in order to avoid plasma-induced damage during a conventional Reactive-ion Etching process. The SiGe stressors were epitaxially grown on the recesses to simulate strained Ge n-channel Metal–Insulator–Semiconductor Field-Effect Transistors (MISFETs) having high electron mobility. A micro-Raman spectroscopy measurement revealed tensile strain in the narrow Ge regions which became higher for narrower regions. Tensile strain of up to 1.2% was evaluated from the measurement under an assumption of uniaxial strain configuration. These results strongly suggest that higher electron mobility than the upper limit for a Si-MOSFET is obtainable in short-channel strained Ge-nMISFETs with the embedded SiGe stressors.