P+/n junction leakage in thin selectively grown Ge-in-STI substrates

This work analyses ultra-shallow pFET junctions in 330 nm-thin germanium virtual substrates, selectively grown in the active regions of Shallow Trench Isolation (STI) patterned silicon wafers. The area leakage is 5–10 times higher than similar junctions in thick Ge virtual substrates if a Post-Growth (PG) anneal is done to reduce the density of threading dislocations. On the other hand, there is a factor of 10 lower perimeter leakage, thanks to the presence of the STI. The dominant generation mechanism is Trap-Assisted Tunneling up to 1 V reverse bias, both for the area- and perimeter-generated leakage, as has been confirmed by measurements at elevated temperatures. Negligible frequency dispersion is found for reverse biases below 3 V. However, at high reverse bias, significant frequency dispersion of the junction capacitance is found, which can be attributed to a higher defect density near the Ge/Si interface.