Reliability study of through-silicon via (TSV) copper filled interconnects

Through-silicon vias (TSVs) have been extensively studied because of their ability to achieve chip stacking for enhanced system performance. The fabrication process is becoming somewhat mature. However, reliability issues need to be addressed in order for an eventual transition from laboratory to production. In our laboratory, vias with tapered sidewalls are formed through a modified Bosch process using deep reactive ion etching (DRIE). Vias are lined with silicon dioxide using plasma enhanced chemical vapor deposition (PECVD) followed by sputter deposited titanium barrier and copper seed layers before filling with a reverse pulse copper electroplating process. Following attachment of the process wafer to a carrier wafer, the process wafer is thinned from the backside by a combination of mechanical methods and reactive ion etching (RIE). Fabricated vias are subjected to thermal cycling with temperatures ranging from − 25 °C to 125 °C. For via chains, erratic changes in resistance upon temperature cycling indicated a problem with the wire bonds used to connect the sample to the test fixture. Test methods were modified to avoid wire bonding and form the basis of reliability studies presented in this paper. TSVs are shown to be stable with small increases in measured resistance for 200 cycles. In addition, small changes in resistance are observed when vias are held at elevated temperatures for extended periods of time.