High aspect ratio via etch development for Cu nails in 3-D-stacked ICs

In this study the etch development of high aspect ratio vias in Si for the fabrication of Cu nails is described. To enable subsequent metallisation, these vias need to meet strict requirements with respect to uniformity, slope, sidewall roughness and undercut. For aspect ratios up to 5 a SiO2 hard mask based SF6/O2 etch approach is used. For aspect ratios up to 10, a resist based passivation polymer type etch approach with C4F8/SF6 was used to successfully pattern vias in Si. Typical problems of this process and optimization to overcome the issues are described.