Effect of grain growth stress and stress gradient on stress-induced voiding in damascene Cu/low-k interconnects for ULSI

The dependence of annealing temperature on stress and microstructure in damascene Cu was examined by X-ray diffraction and transmission electron microscopy. The measured hydrostatic stress was found to increase with increasing annealing temperature in the case of narrow lines. Microstructure analysis using TEM revealed that the grain sizes increased with increasing annealing temperature. Also, the line width dependence of stress in Cu/low-k was compared with that of Cu/SiO2. Although the measured hydrostatic stress of Cu/low-k is somewhat lower than that of Cu/SiO2, the differences in stress between narrow line and wide lines is much larger. Through finite element analysis, the stress gradient between via and line is higher for the case of Cu/low-k. In addition, it was found that the stress gradient is more important than stress itself when low-k is used as dielectric materials because void formation cannot effectively relax the strain energy of the system. This stress gradient between via and line, which is the driving force of vacancy diffusion, is larger when the low-k with lower stiffness and higher thermal expansion is used for dielectric layer. For this reason, it is suggested that the Cu/low-k can be more vulnerable to stress-induced voiding.