The effect of line width on stress-induced voiding in Cu dual damascene interconnects

The influence of M1 (lower level Cu) line width on stress-induced voiding (SIV) behavior of copper dual damascene interconnects was investigated by stress migration test at 200 °C and finite element analysis (FEA). M1 line width under study ranged from 200 nm to 1000 nm, whereas the M2 line width was fixed to be 3 μm. The normalized change in resistance indicated that the via-line structures with larger M1 line width were more susceptible to SIV. Failure analysis utilizing focus ion beam (FIB) showed that voids were formed in the via bottom region for samples with M1 line width less than 280 nm. However, voids were found at the Si3N4/M1 Cu interface near the via bottom if M1 line width is larger than 280 nm.To further understand the underlying physics of SIV, three dimensional finite element models were built to simulate the hydrostatic stress distribution in the via-line structures. It was found that the stress gradient in the length direction, gradσl, was not sensitive to M1 line width, however, the stress gradient in the line width direction, gradσw, was found to increase with M1 line widths. It is thus proposed that in addition to the active diffusion volume, it is the gradσw that further favors the migration of voids (or vacancies) along the Si3N4/M1 Cu interface and subsequent accumulation of the voids near the via bottom leading to a much higher resistance change at larger M1 widths.