A study of the influence of the annealing processes and interfaces with deposited SiO2 from tetra-ethoxy-silane for reducing the thermal budget in the gate definition of 4H–SiC devices

4H–SiC metal-oxide-semiconductor capacitors have been constructed using deposited SiO2 from tetra-ethoxy-silane (TEOS) in the gate process fabrication. The effect of prior deposition interfacial “low temperature” (when compared with a standard thermal oxidation) oxidation (O2 and N2O) and SiO2-TEOS post-deposition annealings (N2, O2, N2O and Ar) has been analyzed. The low temperature interfacial thermal oxidation appears to be the key ingredient for obtaining enhanced gate dielectrics with the TEOS as a means to increase the total thickness from a practical standpoint reducing further the thermal stress and carbon liberation from SiC surface. 4H–SiC metal-oxide-semiconductor field-effect transistors have been fabricated using these oxides and the experimental results show a drastic improvement of the field-effect channel mobility (up to 40 cm2/Vs) with a significant reduction of the sub-threshold swing.