Growth of low defect density GaP layers on Si substrates within the critical thickness by optimized shutter sequence and post-growth annealing

We have developed a growth procedure for realizing a low defect density GaP layer on an Si substrate. The growth procedure consists of two parts. One is the post-growth annealing for the annihilation of stacking faults (SFs). We have investigated an annihilation mechanism with molecular beam epitaxy grown GaP layers. 1-monolayer-thick SFs typically generate from the GaP/Si interface in a non-annealed GaP layer. In a 700 °C annealed GaP layer, generation points of these SFs tend to shift toward the GaP surface. In a 730 °C annealed GaP layer, SFs density is effectively decreased. These results suggest that SFs are annihilated through the climb motion of two partial dislocations during the post-growth annealing. Another one is the optimized shutter sequence for migration enhanced epitaxy. We have revealed that it is effective for the suppression of both three-dimensional growth and melt-back etching to increase in a stepwise manner the number of supplied Ga atoms per cycle. As a result, the generation of threading dislocations and pits is remarkably suppressed. A root mean square surface roughness of 0.13 nm is obtained within the critical thickness. We have estimated etch pit density (EPD) to be ∼7×105 cm−2 with a GaPN/GaP/Si structure. To the best of our knowledge, this value is same as that of commercially available GaP substrates and is the lowest one in the EPD of GaP/Si heteroepitaxy.