Calculation from the current–voltage and capacitance–voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au–Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au–Sb structure has demonstrated clearly rectifying behaviour by the current–voltage (I–V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au–Sb structure have been calculated from the forward bias I–V and reverse bias C−2–V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φb = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I–V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (Rs) effect has been observed. The values of Rs obtained from dV/d(lnI)–I and H(I)–I plots are near to each others (Rs = 182.24 Ω and Rs = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C−2 -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (Nss) of the device has been obtained from the forward bias I–V characteristics. It has been seen that, the Nss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.