Current switching ratio optimization using dual pocket doping engineering

This paper presents a smart idea to maximize current switching ratio of cylindrical gate tunnel FET (CGT) by growing pocket layers in both source and channel region. The pocket layers positioned in the source and channel of the device provides significant improvement in ON-state and OFF-state current respectively. The dual pocket doped cylindrical gate TFET (DP-CGT) exhibits much superior performance in term of drain current, transconductance and current ratio as compared to conventional CGT, channel pocket doped CGT (CP-CGT) and source pocket doped CGT (SP-CGT). Further, the current ratio has been optimized w.r.t. width and instantaneous position both the pocket layers. The much improved current ratio and low power consumption makes the proposed device suitable for low-power and high speed application. The simulation work of DP-CGT is done using 3D Sentaurus TCAD device simulator from Synopsys.