A novel 4H-SiC MESFET with multi-recessed p-buffer layer for high energy-efficiency applications

In this paper, a novel structure named 4H-SiC metal semiconductor field effect transistor with multi-recessed p-buffer layer named MRB MESFET is proposed and simulated. The design of the new structure takes the power added efficiency into account to reduce energy consumption. The channel is assisted to deplete further and the electric field in the drift region for the new structure is modulated by utilizing a multi-recessed p-buffer layer. Thus, the superior gate-source capacitance is obtained and the larger saturation drain current and breakdown voltage are achieved compared with the double-recessed p-buffer layer structure named DRB MESFET. The simulated results demonstrate that the breakdown voltage and the saturation drain current of the MRB MESFET are about 57.89% and 5.63% greater than that of the DRB MESFET. There is an improvement of 86.5% in the maximum output power density for the proposed structure compared with that of the DRB MESFET when the both RF characteristics are similar to. The related structure parameters m = 0.10 μm, n = 0.20 μm are optimized at the beneficial maximum output power density (Pmax), cut-off frequency (fT) and power added efficiency (PAE). All the results show that the advantages and the potential capacities of the MRB MESFET are greater than the DRB MESFET.