Polycrystalline-silicon thin-film transistor fabricated with Cu gate controlled morphology by plating mode

A planarized copper gate thin-film transistor (TFT) using metal-induced laterally-crystallized polycrystalline‑silicon (poly-Si) was fabricated and characterized in this study. The planarized copper gate was able to structurally alleviate the drawbacks of copper and enhance stability to adapt in TFTs. Moreover, the surface of copper was systematically investigated by an electroplating process involving leveling additives such as thiourea and chloride in acidic sulphate-plating baths. These additives can improve surface morphology and ensure a smoother surface of the copper gate, which influence the electrical property of poly-Si TFT while reducing the surface roughness scattering effect. As the gate surface morphology was enhanced, the device exhibited superior electrical characteristics in field-effect mobility, on/off current ratio, and subthreshold slope.