Dielectric relaxation dependent memory elements in pentacene/[6,6]-phenyl-C61-butyric acid methyl ester bi-layer field effect transistors

We fabricate a pentacene/[6,6]-phenyl-C61-butyric acid methyl ester (PCBM) bi-layer field effect transistor (FET) featuring large hysteresis that can be used as memory elements. Intentional introduction of excess electron traps in a PCBM layer by exposure to air caused large hysteresis in the FET. The memory window, characterized by the threshold voltage difference, increased upon exposure to air and this is attributed to an increase in the number of electron trapping centers and (or) an increase in the dielectric relaxation time in the underlying PCBM layer. Decrease in the electron conduction in the PCBM close to the SiO2 gate dielectric upon exposure to air is consistent with the increase in the dielectric relaxation time, ensuring that the presence of large hysteresis in the FET originates from electron trapping at the PCBM not at the pentacene.