A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the Silicon-On-Insulator substrate

• Improving BV and reducing Ron,sp are the research hot topics for power MOSFETs.
• A novel double-gate SOI LDMOS with multiple buried p-layers is proposed.
• For the proposed device, Ron,sp is reduced by 52.5% with BV increasing by 36.4%.

A novel double-gate SOI LDMOS with multiple buried p-layers in the drift region (MBP SOI LDMOS) is proposed in this paper. MBP SOI LDMOS has two gates, the planar gate and the trench gate. The big feature of MBP LDMOS is the multiple buried p-layers with intervals in the drift region which is an arithmetic progression and decreases successively. Firstly, double gates of the structure form dual current conduction channels, leading to a low specific on-resistance (Ron,sp). Secondly, the multiple buried p-layers form a more significant triple RESURF effect, which not only increases the drift doping concentration but also modulates the electric field of the drift region, resulting in a low Ron,sp and a high breakdown voltage (BV). MBP SOI LDMOS is thus owning a reduced Ron,sp and an improved BV. The effects of structure parameters on the device performances are investigated. Compared with the conventional SOI LDMOS, the Ron,sp of MBP SOI LDMOS is reduced by 52.5% with BV increasing by 36.4% at the same 16-μm-drift region.