Anomalous degradation behaviors under illuminated gate bias stress in a-Si:H thin film transistor

• There is abnormal VT shift induced by illuminated gate bias stress in a-Si:H thin film transistors.
• Electron–hole pair is generated via trap-assisted photoexcitation.
• Abnormal transconductance hump is induced by the leakage current from back channel.
• Charge trapping in the passivation layer is likely due to the fact that a constant voltage has been applied to the top gate.

This study investigates the impact of gate bias stress with and without light illumination in a-Si:H thin film transistors. It has been observed that the I–V curve shifts toward the positive direction after negative and positive gate bias stress due to interface state creation at the gate dielectric. However, this study found that threshold voltages shift negatively and that the transconductance curve maxima are anomalously degraded under illuminated positive gate bias stress. In addition, threshold voltages shift positively under illuminated negative gate bias stress. These degradation behaviors can be ascribed to charge trapping in the passivation layer dominating degradation instability and are verified by a double gate a-Si:H device.