Threshold voltage shift of submicron p-channel MOSFET due to Si surface damage from plasma etching process

We compared performances for transistors produced using both wet and dry etching for non-silicide processes in the CMOS technology. It was found that the dry process for non-silicide area induces the threshold voltage shifting of the pMOS transistor as well as increases the contact resistance on active region. Also, GIDL (gate-induced-drain-leakage) current has a poor junction leakage current compared with the wet etching process. Moreover, the dry etching process changes the doping profile of the P+ junction and the p-channel transistor region. The experiments showed the dry etching process generates the Si–SiO2 interface trap site due to plasma-induced damage.